One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature of their iterative belief propagation decoding, making them amenable to efficient hardware implementation. However, for an arbitrary code construction, the random-like connections between the code's Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads to complex interconnect wiring and routing congestion. In this paper, we present a novel LDPC code design approach, based on the progressive edge growth (PEG) Tanner graph construction, to solve the problem of dense connections between processing nodes. The approach is based on controlling the maximum connection length between processing nodes in order to make fully parallel implementation feasible. The proposed algorithm offers a good compromise between error correction performance and decoder complexity. Simulation results and FPGA-based implementation comparisons are presented to demonstrate the advantages of the proposed LDPC code constructions, and it is shown that, with proper window-constrained node placement design, an improvement of up to 40% in interconnect efficiency is achievable without any significant degradation in error correction capability.
|Number of pages||7|
|Journal||AEU - International Journal of Electronics and Communications|
|State||Published - Jul 2013|
Bibliographical noteFunding Information:
The authors would like to thank King Fahd University of Petroleum & Minerals for supporting this work under Project DSR-IN070376.
- Interconnect complexity
- LDPC codes
- Progressive edge growth
- Routing congestion
ASJC Scopus subject areas
- Electrical and Electronic Engineering