VLSI implementation of a systolic database machine for relational algebra and hashing

Khaled M. Elleithy; Magdy A. Bayoumi; Lois M. Delcambre

doi:10.1016/0167-9260(91)90018-G

VLSI implementation of a systolic database machine for relational algebra and hashing

Khaled M. Elleithy^*
, Magdy A. Bayoumi
, Lois M. Delcambre

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3υ CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.

Original language	English
Pages (from-to)	169-190
Number of pages	22
Journal	Integration, the VLSI Journal
Volume	11
Issue number	2
DOIs	https://doi.org/10.1016/0167-9260(91)90018-G
State	Published - Apr 1991

Bibliographical note

Funding Information:
The first author gratefully acknowledges support from the King Fahd University of Petroleum and Minerals. The second author acknowledges the support by the National Science Foundation under Grant MIP-8809811.

Keywords

Database machines
VLSI
hashing
relational algebra
systolic arrays

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1016/0167-9260(91)90018-G

Cite this

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title = "VLSI implementation of a systolic database machine for relational algebra and hashing",

abstract = "Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3υ CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.",

keywords = "Database machines, VLSI, hashing, relational algebra, systolic arrays",

author = "Elleithy, \{Khaled M.\} and Bayoumi, \{Magdy A.\} and Delcambre, \{Lois M.\}",

note = "Funding Information: The first author gratefully acknowledges support from the King Fahd University of Petroleum and Minerals. The second author acknowledges the support by the National Science Foundation under Grant MIP-8809811.",

year = "1991",

month = apr,

doi = "10.1016/0167-9260(91)90018-G",

language = "English",

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journal = "Integration, the VLSI Journal",

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AU - Elleithy, Khaled M.

AU - Bayoumi, Magdy A.

AU - Delcambre, Lois M.

N1 - Funding Information: The first author gratefully acknowledges support from the King Fahd University of Petroleum and Minerals. The second author acknowledges the support by the National Science Foundation under Grant MIP-8809811.

PY - 1991/4

Y1 - 1991/4

N2 - Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3υ CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.

AB - Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3υ CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.

KW - Database machines

KW - VLSI

KW - hashing

KW - relational algebra

KW - systolic arrays

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JF - Integration, the VLSI Journal

IS - 2

ER -

VLSI implementation of a systolic database machine for relational algebra and hashing

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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