VLSI design and implementation of systolic tree queues

Sadiq M. Sait; Muhammad A.A. Khalid

doi:10.1016/0141-9331(95)96908-N

VLSI design and implementation of systolic tree queues

Sadiq M. Sait^*
, Muhammad A.A. Khalid

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue.

Original language	English
Pages (from-to)	139-146
Number of pages	8
Journal	Microprocessors and Microsystems
Volume	19
Issue number	3
DOIs	https://doi.org/10.1016/0141-9331(95)96908-N
State	Published - 1995

Bibliographical note

Funding Information:
The authors acknowledge King Fahd University of Petroleum and Minerals for support of this work. We would like to thank Dr H Youssef and Dr M Abd-EI-Barr for their comments and discussion that helped to improve the quality of this manuscript.

Keywords

VLSI design
automated layout
systolic tree architecture

ASJC Scopus subject areas

Software
Hardware and Architecture
Computer Networks and Communications
Artificial Intelligence

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10.1016/0141-9331(95)96908-N

Cite this

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title = "VLSI design and implementation of systolic tree queues",

abstract = "A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue.",

keywords = "VLSI design, automated layout, systolic tree architecture",

author = "Sait, \{Sadiq M.\} and Khalid, \{Muhammad A.A.\}",

note = "Funding Information: The authors acknowledge King Fahd University of Petroleum and Minerals for support of this work. We would like to thank Dr H Youssef and Dr M Abd-EI-Barr for their comments and discussion that helped to improve the quality of this manuscript.",

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AU - Sait, Sadiq M.

AU - Khalid, Muhammad A.A.

N1 - Funding Information: The authors acknowledge King Fahd University of Petroleum and Minerals for support of this work. We would like to thank Dr H Youssef and Dr M Abd-EI-Barr for their comments and discussion that helped to improve the quality of this manuscript.

PY - 1995

Y1 - 1995

N2 - A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue.

AB - A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue.

KW - VLSI design

KW - automated layout

KW - systolic tree architecture

UR - https://www.scopus.com/pages/publications/0029293374

U2 - 10.1016/0141-9331(95)96908-N

DO - 10.1016/0141-9331(95)96908-N

M3 - Article

AN - SCOPUS:0029293374

SN - 0141-9331

VL - 19

SP - 139

EP - 146

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

IS - 3

ER -

VLSI design and implementation of systolic tree queues

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this