Transistor-level based defect tolerance for reliable nanoelectronics

Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations


Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quadded-transistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defecttolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

Original languageEnglish
Title of host publicationAICCSA 08 - 6th IEEE/ACS International Conference on Computer Systems and Applications
Number of pages8
StatePublished - 2008

Publication series

NameAICCSA 08 - 6th IEEE/ACS International Conference on Computer Systems and Applications

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Science Applications
  • Control and Systems Engineering


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