Transistor-level based defect-tolerance for reliable nanoelectronics

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. A promising defect tolerance approach is one combining expensive but reliable gates with cheap but unreliable gates. One approach for increasing reliability of gates is by adding redundancy at the transistor-level implementation. In this chapter, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by a quadded-transistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to four to five times more transistor defect probability) and at reduced area overhead. The proposed approach can be effective in enhancing the reliability of Triple-modular- redundancy based defect tolerance approaches by enhancing the reliability of voter gates implementation.