Abstract
We present a timing driven floorplanning program for general cell layouts. The approach used combines quality of force directed approach with that of constraint graph approach. A floorplan solution is produced in two steps. First a timing and connectivity driven topological arrangement is obtained using a force directed approach. In the second step, the topological arrangement is transformed into a legal floorplan. The objective of the second step is to minimize the overall area of the floorplan. The floorplanner is validated with circuits of sizes varying from 7 to 125 blocks.
| Original language | English |
|---|---|
| Pages | 156-161 |
| Number of pages | 6 |
| State | Published - 1995 |
ASJC Scopus subject areas
- Control and Systems Engineering
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