Timing-driven global routing for standard-cell VLSI design

Computer Science

• Global Routing 100%
• Standards 100%
• Design 100%
• Solution Quality 66%
• Tabu Search 66%
• Programs 66%
• Preferential Treatment 33%
• Interconnect Delay 33%
• Roles 33%
• Routers 33%
• Simulated Annealing 33%
• Routing Solution 33%

Engineering

• Design 100%
• Standard Cell 100%
• Networks (Circuits) 66%
• Performance 66%
• VLSI Circuits 33%
• Interconnection 33%
• Clock Rate 33%
• Routing Solution 33%
• Iterative Improvement 33%
• Experiments 33%
• Interconnects 33%