Timing-driven global routing for standard-cell VLSI design

For VLSI designs, interconnect delays play an important role in determining the performance of the circuits as they can make it impossible to achieve the required clock rate. Nowadays, it is rare to find a placement program that does not take into consideration timing issues of the circuit. However, routing did not receive similar attention. We believe that timing of the layout can be further improved if timing critical nets are given preferential treatment during routing. In this paper, we present the implementation of a timing-driven global router program for a two layer standard cell VLSI design. An iterative improvement technique called Tabu Search (TS) is used to improve the initial global routing solution. The solution quality is measured in terms of path delays, interconnection length and layout area. Results of experiments on practical VLSI circuits reveal substantial improvement in terms of timing performance. Furthermore, when compared with Simulated Annealing, Tabu Search exhibited superior behavior with respect to run time and solution quality.