Testability Implications of Performance-Driven Logic Synthesis

Thomas E. Marchok; Aiman El-Maleh; Janusz Rajski; Wojciech Maly

doi:10.1109/54.386003

Testability Implications of Performance-Driven Logic Synthesis

Thomas E. Marchok
, Aiman El-Maleh
, Janusz Rajski
, Wojciech Maly

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation.

Original language	English
Pages (from-to)	32-39
Number of pages	8
Journal	IEEE Design and Test of Computers
Volume	12
Issue number	2
DOIs	https://doi.org/10.1109/54.386003
State	Published - 1995
Externally published	Yes

Bibliographical note

Funding Information:
Semiconductor Research Corporatio (contract 94-DC468), Intel, and a Naturi Sciences and Engineering Researc Council of Canada research grant suppoi ed this work.

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/54.386003

Cite this

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title = "Testability Implications of Performance-Driven Logic Synthesis",

abstract = "Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation.",

author = "Marchok, \{Thomas E.\} and Aiman El-Maleh and Janusz Rajski and Wojciech Maly",

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AU - Rajski, Janusz

AU - Maly, Wojciech

N1 - Funding Information: Semiconductor Research Corporatio (contract 94-DC468), Intel, and a Naturi Sciences and Engineering Researc Council of Canada research grant suppoi ed this work.

PY - 1995

Y1 - 1995

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AB - Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation.

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DO - 10.1109/54.386003

M3 - Article

AN - SCOPUS:0029323232

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JO - IEEE Design and Test of Computers

JF - IEEE Design and Test of Computers

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ER -

Testability Implications of Performance-Driven Logic Synthesis

Abstract

Bibliographical note

ASJC Scopus subject areas

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