Test set compression through alternation between deterministic and pseudorandom test patterns

Ahmad A. Al-Yamani, Edward J. McCluskey

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without explicitly loading a seed. The ATPG process is tuned to target only undetected faults as the PRPG goes through its natural sequence which is maximally used to generate useful test patterns. The test application procedure is slightly modified to enable higher flexibility and more reduction in tester storage and test time. The results of applying the technique show up to 90% reduction in tester storage and 80% reduction in test time compared to classic reseeding. They also show 70% improvement in defect coverage when the technique is emulated on test chips with real defects.

Original languageEnglish
Pages (from-to)513-521
Number of pages9
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume26
Issue number5
DOIs
StatePublished - Oct 2010

Bibliographical note

Funding Information:
Acknowledgments This work was supported by King Fahd University of Petroleum and Minerals and by LSI Logic under contract No. 16517.

Keywords

  • BIST
  • Built-in self-test
  • DFT
  • Design-for-testability
  • Deterministic BIST
  • Pseudorandom test
  • Reseeding
  • Scan testing
  • Test set compression

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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