Tabu search based circuit optimization

In this paper we address the problem of optimizing mixed CMOS/BiCMOS circuits. The problem, formulated as a constrained combinatorial optimization problem is addressed using a tabu search algorithm. Initially a random approach is adopted for selecting among available solutions. Further, as an alternative competing solution the concepts of simulated evolution are applied to classical tabu search (CTS). This allows for a stochastic criterion for selecting among available solutions as compared to the random approach of CTS. Only gates on the critical sensitizable paths are considered for optimization. Such a strategy leads to sizeable circuit speed improvement with minimum increase in the overall circuit capacitance. Compared to earlier approaches, the presented techniques produce circuits with remarkable increase in speed (greater than 20%) for very small increase in overall circuit capacitance (less than 3%).