Systolic interconnection network

Hasan Cam

Systolic interconnection network

Hasan Cam^*

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, a log₂N -stage self-routing rearrangeable network with N inputs/outputs is presented. A self-routing algorithm called the breadth-first destination tag routing algorithm is proposed to realize any permutation of N inputs in a pipelined fashion. This self-routing algorithm maximizes the utilization of every switch of the network, along with a fair load balancing in routing data packets to their destinations. It takes O (log₂N) time to realize any permutation of packets on the network. The switch-level and VLSI-level hardware complexities of the network are O (N log₂N) and O (N²/log₂^3/2N), respectively.

Original language	English
Pages	of 3/-
State	Published - 1994
Externally published	Yes

ASJC Scopus subject areas

General Engineering

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title = "Systolic interconnection network",

abstract = "In this paper, a log2N -stage self-routing rearrangeable network with N inputs/outputs is presented. A self-routing algorithm called the breadth-first destination tag routing algorithm is proposed to realize any permutation of N inputs in a pipelined fashion. This self-routing algorithm maximizes the utilization of every switch of the network, along with a fair load balancing in routing data packets to their destinations. It takes O (log2N) time to realize any permutation of packets on the network. The switch-level and VLSI-level hardware complexities of the network are O (N log2N) and O (N2/log23/2N), respectively.",

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AB - In this paper, a log2N -stage self-routing rearrangeable network with N inputs/outputs is presented. A self-routing algorithm called the breadth-first destination tag routing algorithm is proposed to realize any permutation of N inputs in a pipelined fashion. This self-routing algorithm maximizes the utilization of every switch of the network, along with a fair load balancing in routing data packets to their destinations. It takes O (log2N) time to realize any permutation of packets on the network. The switch-level and VLSI-level hardware complexities of the network are O (N log2N) and O (N2/log23/2N), respectively.

UR - https://www.scopus.com/pages/publications/0028699996

M3 - Paper

AN - SCOPUS:0028699996

SP - of 3/-

ER -

Systolic interconnection network

Abstract

ASJC Scopus subject areas

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