Systematic scan reconfiguration

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

We present a new test data compression technique that achieves 10x to 40x compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages738-743
Number of pages6
DOIs
StatePublished - 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Systematic scan reconfiguration'. Together they form a unique fingerprint.

Cite this