Super-Resolution CNN Accelerator on Low-Cost Zynq-7000 Series SoC-based FPGA

This work presents an implementation of a super-resolution (SR) convolutional neural network (CNN) accelerator on low-cost Zynq-7000 series SoC-based FPGA. On Xilinx FPGA boards, C programming is employed for deploying a trained SR CNN model using Vivado high-level synthesis. Key optimizations are strategically implemented to efficiently utilize the limited on-board resources, leading to the creation of an optimized IP core. With deterministic latency, the system consistently delivers high-resolution images with a processing timing of 4.35 ns. The outcomes not only showcase the viability but also the effectiveness of implementing intricate machine learning models on cost-effective FPGA platforms. This underscores the potential for broader applications in fields that demand real-time machine learning execution.