Abstract
A new technology mapper (SELF-Map) for Look-U Table (LUT) based Field Programmable Gate Arrays (FPGAs) is described. SELF-Map is based on the Stochastic Evolution (SE) algorithm. The state space model of the problem is defined and suitable cost function which allows optimization for area, delay, or area-delay combinations is proposed. Experimental results show that SELF-Map has an overall better performance compared to other algorithms reported in the literature.
| Original language | English |
|---|---|
| Pages (from-to) | 380-385 |
| Number of pages | 6 |
| Journal | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| State | Published - 1998 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering