STATISTICS FOR IMPROVEMENT OF IC PROCESS CONTROL.

The use of test patterns is a valuable vehicle for monitoring production of large scale integrated circuit wafers with respect to the expected systems performance of the circuits. A basic limitation in current procedures is the manner in which tested parameter data is extrapolated from test pattern locations to other chips on the wafer. This paper describes a new procedure based on a ″test″ wafer which enables one to develop a statistical algorithm for improved parameter extrapolation.