Statistical modelling of analog circuits for test metrics computation

Kamel Beznia; Ahcene Bounceur; Salvador Mir; Reinhardt Euler

doi:10.1109/DTIS.2013.6527772

Statistical modelling of analog circuits for test metrics computation

Kamel Beznia, Ahcene Bounceur, Salvador Mir, Reinhardt Euler

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (T_E) and Yield Loss (Y_L). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.

Original language	English
Title of host publication	Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013
Pages	25-29
Number of pages	5
DOIs	https://doi.org/10.1109/DTIS.2013.6527772
State	Published - 2013
Externally published	Yes
Event	2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 - Abu Dhabi, United Arab Emirates Duration: 26 Mar 2013 → 28 Mar 2013

Publication series

Name	Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013

Conference

Conference	2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	26/03/13 → 28/03/13

Keywords

Analog test
RF test
mixed-signal test
statistical model
test metrics estimation
theory of Copulas

ASJC Scopus subject areas

Control and Systems Engineering

Access to Document

10.1109/DTIS.2013.6527772

Cite this

Beznia, K., Bounceur, A., Mir, S., & Euler, R. (2013). Statistical modelling of analog circuits for test metrics computation. In Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 (pp. 25-29). Article 6527772 (Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013). https://doi.org/10.1109/DTIS.2013.6527772

Beznia, Kamel ; Bounceur, Ahcene ; Mir, Salvador et al. / Statistical modelling of analog circuits for test metrics computation. Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013. 2013. pp. 25-29 (Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013).

@inproceedings{ff2b8257104040269b645c335ab97042,

title = "Statistical modelling of analog circuits for test metrics computation",

abstract = "Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (YL). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.",

keywords = "Analog test, RF test, mixed-signal test, statistical model, test metrics estimation, theory of Copulas",

author = "Kamel Beznia and Ahcene Bounceur and Salvador Mir and Reinhardt Euler",

year = "2013",

doi = "10.1109/DTIS.2013.6527772",

language = "English",

isbn = "9781467360388",

series = "Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013",

pages = "25--29",

booktitle = "Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013",

note = "2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 ; Conference date: 26-03-2013 Through 28-03-2013",

}

Beznia, K, Bounceur, A, Mir, S & Euler, R 2013, Statistical modelling of analog circuits for test metrics computation. in Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013., 6527772, Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013, pp. 25-29, 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013, Abu Dhabi, United Arab Emirates, 26/03/13. https://doi.org/10.1109/DTIS.2013.6527772

Statistical modelling of analog circuits for test metrics computation. / Beznia, Kamel; Bounceur, Ahcene; Mir, Salvador et al.
Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013. 2013. p. 25-29 6527772 (Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Statistical modelling of analog circuits for test metrics computation

AU - Beznia, Kamel

AU - Bounceur, Ahcene

AU - Mir, Salvador

AU - Euler, Reinhardt

PY - 2013

Y1 - 2013

N2 - Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (YL). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.

AB - Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (YL). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.

KW - Analog test

KW - RF test

KW - mixed-signal test

KW - statistical model

KW - test metrics estimation

KW - theory of Copulas

UR - https://www.scopus.com/pages/publications/84881150914

U2 - 10.1109/DTIS.2013.6527772

DO - 10.1109/DTIS.2013.6527772

M3 - Conference contribution

AN - SCOPUS:84881150914

SN - 9781467360388

T3 - Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013

SP - 25

EP - 29

BT - Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013

T2 - 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013

Y2 - 26 March 2013 through 28 March 2013

ER -

Beznia K, Bounceur A, Mir S, Euler R. Statistical modelling of analog circuits for test metrics computation. In Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013. 2013. p. 25-29. 6527772. (Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013). doi: 10.1109/DTIS.2013.6527772

Statistical modelling of analog circuits for test metrics computation

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this