State identification, existence of sequences and machine classification

An essential part of fault analysis of sequential circuits is the identification of their initial or final state by use of synchronizing, homing and distinguishing sequences. Algorithms are developed for deciding the existence of these sequences. They make use of the well-known compatibility table technique universally employed for the minimization of state sets. The technique is then expanded to permit the classification of machines based on these three sequences. It unifies the various known graph theoretical methods and presents new insights into the structure theory of finite state machines.