TY - GEN
T1 - Split-Gate Logic circuits for multi-threshold technologies
AU - Elrabaa, Muhammad E.S.
AU - Elmasry, Mohamed I.
PY - 2001
Y1 - 2001
N2 - A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SG-DVT) logic, are devised. Their performance is compared to that of all-low-Vt, all-high-Vt, and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits, lower leakage (both stand-by and active) than other dual-Vt circuits, and lower leakage dependency on logic block input patterns.
AB - A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SG-DVT) logic, are devised. Their performance is compared to that of all-low-Vt, all-high-Vt, and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits, lower leakage (both stand-by and active) than other dual-Vt circuits, and lower leakage dependency on logic block input patterns.
UR - https://www.scopus.com/pages/publications/84888053498
U2 - 10.1109/ISCAS.2001.922358
DO - 10.1109/ISCAS.2001.922358
M3 - Conference contribution
AN - SCOPUS:84888053498
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 798
EP - 801
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
ER -