Split-gate logic circuits for multi-threshold technologies

A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SG-DVT) logic, are devised. Their performance is compared to that of all-low-Vt, all-high-Vt, and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits, lower leakage (both stand-by and active) than other dual-Vt circuits, and lower leakage dependency on logic block input patterns.