Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches

Marif Daula Siddique; Asif Mustafa; Adil Sarwar; Saad Mekhilef; Noraisyah Binti Mohamed Shah; Mehdi Seyedamahmousian; Alex Stojcevski; Ben Horan; Koki Ogura

doi:10.1109/ETECHNXT.2018.8385334

Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches

Marif Daula Siddique
, Asif Mustafa
, Adil Sarwar
, Saad Mekhilef
, Noraisyah Binti Mohamed Shah
, Mehdi Seyedamahmousian
, Alex Stojcevski
, Ben Horan
, Koki Ogura

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

24 Scopus citations

Abstract

Multilevel Inverters have shaped a new trend of importance in industry and research. A new topology of multilevel inverter is proposed in this paper which can be operated in symmetrical and asymmetrical modes. The proposed topology produces 7-level and 13-level staircase output voltage waveform for symmetrical and asymmetrical configuration respectively using only 10 switches. The gate signals for the different switches are produced employing the fundamental frequency switching technique. The topology achieves better performance using a lower minimum number of components in comparison to conventional inverters. These improvements result in reduced system cost and size. Simulations are carried out using MATLAB/SIMULINK environment and experimental implementation using laboratory prototype module have ascertained the performance and operation of the proposed topology.

Original language	English
Title of host publication	2018 IEEMA Engineer Infinite Conference, eTechNxT 2018
Editors	Urooj Shabana Urooj, Subrata Mukhopadhyay
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781538611388
DOIs	https://doi.org/10.1109/ETECHNXT.2018.8385334
State	Published - 13 Jun 2018

Publication series

Name	2018 IEEMA Engineer Infinite Conference, eTechNxT 2018

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

asymmetrical
fundamental frequency switching
H-bridge
Multilevel inverter
symmetrical
total harmonic distortion

ASJC Scopus subject areas

Artificial Intelligence
Energy Engineering and Power Technology
Renewable Energy, Sustainability and the Environment
Electrical and Electronic Engineering
Control and Optimization

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10.1109/ETECHNXT.2018.8385334

Cite this

Siddique, M. D., Mustafa, A., Sarwar, A., Mekhilef, S., Shah, N. B. M., Seyedamahmousian, M., Stojcevski, A., Horan, B., & Ogura, K. (2018). Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches. In U. S. Urooj, & S. Mukhopadhyay (Eds.), 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018 (pp. 1-6). (2018 IEEMA Engineer Infinite Conference, eTechNxT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ETECHNXT.2018.8385334

Siddique, Marif Daula ; Mustafa, Asif ; Sarwar, Adil et al. / Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches. 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018. editor / Urooj Shabana Urooj ; Subrata Mukhopadhyay. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-6 (2018 IEEMA Engineer Infinite Conference, eTechNxT 2018).

@inproceedings{524856f9387648fab4a62d3abc1da777,

title = "Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches",

abstract = "Multilevel Inverters have shaped a new trend of importance in industry and research. A new topology of multilevel inverter is proposed in this paper which can be operated in symmetrical and asymmetrical modes. The proposed topology produces 7-level and 13-level staircase output voltage waveform for symmetrical and asymmetrical configuration respectively using only 10 switches. The gate signals for the different switches are produced employing the fundamental frequency switching technique. The topology achieves better performance using a lower minimum number of components in comparison to conventional inverters. These improvements result in reduced system cost and size. Simulations are carried out using MATLAB/SIMULINK environment and experimental implementation using laboratory prototype module have ascertained the performance and operation of the proposed topology.",

keywords = "asymmetrical, fundamental frequency switching, H-bridge, Multilevel inverter, symmetrical, total harmonic distortion",

author = "Siddique, \{Marif Daula\} and Asif Mustafa and Adil Sarwar and Saad Mekhilef and Shah, \{Noraisyah Binti Mohamed\} and Mehdi Seyedamahmousian and Alex Stojcevski and Ben Horan and Koki Ogura",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2018",

month = jun,

day = "13",

doi = "10.1109/ETECHNXT.2018.8385334",

language = "English",

series = "2018 IEEMA Engineer Infinite Conference, eTechNxT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--6",

editor = "Urooj, \{Urooj Shabana\} and Subrata Mukhopadhyay",

booktitle = "2018 IEEMA Engineer Infinite Conference, eTechNxT 2018",

address = "United States",

}

Siddique, MD, Mustafa, A, Sarwar, A, Mekhilef, S, Shah, NBM, Seyedamahmousian, M, Stojcevski, A, Horan, B & Ogura, K 2018, Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches. in US Urooj & S Mukhopadhyay (eds), 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018. 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-6. https://doi.org/10.1109/ETECHNXT.2018.8385334

Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches. / Siddique, Marif Daula; Mustafa, Asif; Sarwar, Adil et al.
2018 IEEMA Engineer Infinite Conference, eTechNxT 2018. ed. / Urooj Shabana Urooj; Subrata Mukhopadhyay. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-6 (2018 IEEMA Engineer Infinite Conference, eTechNxT 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches

AU - Siddique, Marif Daula

AU - Mustafa, Asif

AU - Sarwar, Adil

AU - Mekhilef, Saad

AU - Shah, Noraisyah Binti Mohamed

AU - Seyedamahmousian, Mehdi

AU - Stojcevski, Alex

AU - Horan, Ben

AU - Ogura, Koki

PY - 2018/6/13

Y1 - 2018/6/13

N2 - Multilevel Inverters have shaped a new trend of importance in industry and research. A new topology of multilevel inverter is proposed in this paper which can be operated in symmetrical and asymmetrical modes. The proposed topology produces 7-level and 13-level staircase output voltage waveform for symmetrical and asymmetrical configuration respectively using only 10 switches. The gate signals for the different switches are produced employing the fundamental frequency switching technique. The topology achieves better performance using a lower minimum number of components in comparison to conventional inverters. These improvements result in reduced system cost and size. Simulations are carried out using MATLAB/SIMULINK environment and experimental implementation using laboratory prototype module have ascertained the performance and operation of the proposed topology.

AB - Multilevel Inverters have shaped a new trend of importance in industry and research. A new topology of multilevel inverter is proposed in this paper which can be operated in symmetrical and asymmetrical modes. The proposed topology produces 7-level and 13-level staircase output voltage waveform for symmetrical and asymmetrical configuration respectively using only 10 switches. The gate signals for the different switches are produced employing the fundamental frequency switching technique. The topology achieves better performance using a lower minimum number of components in comparison to conventional inverters. These improvements result in reduced system cost and size. Simulations are carried out using MATLAB/SIMULINK environment and experimental implementation using laboratory prototype module have ascertained the performance and operation of the proposed topology.

KW - asymmetrical

KW - fundamental frequency switching

KW - H-bridge

KW - Multilevel inverter

KW - symmetrical

KW - total harmonic distortion

UR - https://www.scopus.com/pages/publications/85049857399

U2 - 10.1109/ETECHNXT.2018.8385334

DO - 10.1109/ETECHNXT.2018.8385334

M3 - Conference contribution

AN - SCOPUS:85049857399

T3 - 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018

SP - 1

EP - 6

BT - 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018

A2 - Urooj, Urooj Shabana

A2 - Mukhopadhyay, Subrata

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Siddique MD, Mustafa A, Sarwar A, Mekhilef S, Shah NBM, Seyedamahmousian M et al. Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches. In Urooj US, Mukhopadhyay S, editors, 2018 IEEMA Engineer Infinite Conference, eTechNxT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-6. (2018 IEEMA Engineer Infinite Conference, eTechNxT 2018). doi: 10.1109/ETECHNXT.2018.8385334

Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches

Abstract

Publication series

Bibliographical note

Keywords

ASJC Scopus subject areas

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Cite this