Abstract
This paper presents analysis of the trade off between hardware overhead, runtime, and test data volume when implementing Systematic Scan Reconfiguration using centralized and distributed architectures of the Segmented Addressable Scan, which is an Illinois-Scan based architecture. The results show that the centralized scheme offers better data volume compression, similar ATPG runtime results and lower hardware overhead. The cost with the centralized scheme is in the routing congestion.
| Original language | English |
|---|---|
| Pages (from-to) | 406-414 |
| Number of pages | 9 |
| Journal | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems |
| State | Published - 2005 |
ASJC Scopus subject areas
- General Engineering