Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress

Zeeshan Sarwer; Marif Daula Siddique; Atif Iqbal; Adil Sarwar; Khaliqur Rahman; Saad Mekhilef

doi:10.1109/PEDES49360.2020.9379538

Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress

Zeeshan Sarwer
, Marif Daula Siddique
, Atif Iqbal
, Adil Sarwar
, Khaliqur Rahman
, Saad Mekhilef

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper puts forward a seven-level switched-capacitor multilevel inverter (7L-SCMLI) with boosting features. The main features of the proposed structure are the use of reduced number of switches, lesser value of total standing voltage (TSV). Results obtained by simulation and experimental setup are displayed in the paper to validate the claim. Power loss analysis is done to estimate efficiency. The information regarding harmonic analysis and efficiency comparison is conveyed through various plots. The harmonic analysis shows a THD of 12.19% in the voltage waveform. From the plot of efficiency, the maximum efficiency can be seen near to 98%. The proposed structure of multilevel inverter has been compared with other topologies of similar level on various performance parameters and stands as a good candidate for the industrial applications.

Original language	English
Title of host publication	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728156729
DOIs	https://doi.org/10.1109/PEDES49360.2020.9379538
State	Published - 16 Dec 2020
Event	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020 - Jaipur, India Duration: 16 Dec 2020 → 19 Dec 2020

Publication series

Name	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

Conference

Conference	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020
Country/Territory	India
City	Jaipur
Period	16/12/20 → 19/12/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

Nearest Level Control
SCMLI
Total Standing Voltage

ASJC Scopus subject areas

Electrical and Electronic Engineering
Mechanical Engineering
Control and Optimization
Energy Engineering and Power Technology
Automotive Engineering

Access to Document

10.1109/PEDES49360.2020.9379538

Cite this

Sarwer, Z., Siddique, M. D., Iqbal, A., Sarwar, A., Rahman, K., & Mekhilef, S. (2020). Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress. In 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020 Article 9379538 (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PEDES49360.2020.9379538

Sarwer, Zeeshan ; Siddique, Marif Daula ; Iqbal, Atif et al. / Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress. 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020).

@inproceedings{96fb3a99f96d4371972e02bafec258fb,

title = "Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress",

abstract = "This paper puts forward a seven-level switched-capacitor multilevel inverter (7L-SCMLI) with boosting features. The main features of the proposed structure are the use of reduced number of switches, lesser value of total standing voltage (TSV). Results obtained by simulation and experimental setup are displayed in the paper to validate the claim. Power loss analysis is done to estimate efficiency. The information regarding harmonic analysis and efficiency comparison is conveyed through various plots. The harmonic analysis shows a THD of 12.19\% in the voltage waveform. From the plot of efficiency, the maximum efficiency can be seen near to 98\%. The proposed structure of multilevel inverter has been compared with other topologies of similar level on various performance parameters and stands as a good candidate for the industrial applications.",

keywords = "Nearest Level Control, SCMLI, Total Standing Voltage",

author = "Zeeshan Sarwer and Siddique, \{Marif Daula\} and Atif Iqbal and Adil Sarwar and Khaliqur Rahman and Saad Mekhilef",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020 ; Conference date: 16-12-2020 Through 19-12-2020",

year = "2020",

month = dec,

day = "16",

doi = "10.1109/PEDES49360.2020.9379538",

language = "English",

series = "9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020",

address = "United States",

}

Sarwer, Z, Siddique, MD, Iqbal, A, Sarwar, A, Rahman, K & Mekhilef, S 2020, Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress. in 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020., 9379538, 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020, Institute of Electrical and Electronics Engineers Inc., 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020, Jaipur, India, 16/12/20. https://doi.org/10.1109/PEDES49360.2020.9379538

Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress. / Sarwer, Zeeshan; Siddique, Marif Daula; Iqbal, Atif et al.
9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9379538 (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress

AU - Sarwer, Zeeshan

AU - Siddique, Marif Daula

AU - Iqbal, Atif

AU - Sarwar, Adil

AU - Rahman, Khaliqur

AU - Mekhilef, Saad

PY - 2020/12/16

Y1 - 2020/12/16

N2 - This paper puts forward a seven-level switched-capacitor multilevel inverter (7L-SCMLI) with boosting features. The main features of the proposed structure are the use of reduced number of switches, lesser value of total standing voltage (TSV). Results obtained by simulation and experimental setup are displayed in the paper to validate the claim. Power loss analysis is done to estimate efficiency. The information regarding harmonic analysis and efficiency comparison is conveyed through various plots. The harmonic analysis shows a THD of 12.19% in the voltage waveform. From the plot of efficiency, the maximum efficiency can be seen near to 98%. The proposed structure of multilevel inverter has been compared with other topologies of similar level on various performance parameters and stands as a good candidate for the industrial applications.

AB - This paper puts forward a seven-level switched-capacitor multilevel inverter (7L-SCMLI) with boosting features. The main features of the proposed structure are the use of reduced number of switches, lesser value of total standing voltage (TSV). Results obtained by simulation and experimental setup are displayed in the paper to validate the claim. Power loss analysis is done to estimate efficiency. The information regarding harmonic analysis and efficiency comparison is conveyed through various plots. The harmonic analysis shows a THD of 12.19% in the voltage waveform. From the plot of efficiency, the maximum efficiency can be seen near to 98%. The proposed structure of multilevel inverter has been compared with other topologies of similar level on various performance parameters and stands as a good candidate for the industrial applications.

KW - Nearest Level Control

KW - SCMLI

KW - Total Standing Voltage

UR - https://www.scopus.com/pages/publications/85103885947

U2 - 10.1109/PEDES49360.2020.9379538

DO - 10.1109/PEDES49360.2020.9379538

M3 - Conference contribution

AN - SCOPUS:85103885947

T3 - 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

BT - 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

Y2 - 16 December 2020 through 19 December 2020

ER -

Sarwer Z, Siddique MD, Iqbal A, Sarwar A, Rahman K, Mekhilef S. Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress. In 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9379538. (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020). doi: 10.1109/PEDES49360.2020.9379538

Seven-level switched-capacitor based multilevel inverter with lesser number of power electronic components and reduced voltage stress

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this