Segmenting large traces of inter-process communication with a focus on high performance computing systems

Luay Alawneh*, Abdelwahab Hamou-Lhadj, Jameleddine Hassine

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

The understanding of the interactions among processes of a High Performance Computing (HPC) system can be made easier if trace analysis is used. Traces, however, can be quite large, making it difficult to analyze their content unless some abstraction is provided. This paper presents a novel trace abstraction approach that aims to facilitate the analysis of large execution traces generated from HPC applications. Our approach allows automatic segmentation of large traces into smaller and meaningful clusters that reflect the various execution phases of the traced scenarios. Our approach is based on the application of information theory principles to the analysis of sequences of communication patterns extracted from traces of HPC systems. This work is inspired by recent studies in the field of bioinformatics where several techniques have been proposed to segment DNA sequences into homogeneous sub-domains, where each sub-domain exhibits a certain degree of internal homogeneity. Trace segments can be used in a number of applications such as recovering high-level views of the system behavior and program understanding. We demonstrate the usefulness of our approach by applying it to different traces of hundreds of millions of events, generated from two HPC systems.

Original languageEnglish
Pages (from-to)1-16
Number of pages16
JournalJournal of Systems and Software
Volume120
DOIs
StatePublished - 1 Oct 2016

Bibliographical note

Publisher Copyright:
© 2016 Elsevier Inc.

Keywords

  • Dynamic analysis
  • High performance computing systems
  • Inter-process communication traces
  • Program comprehension
  • Software maintenance
  • Trace abstraction and analysis

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

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