Scan test cost and power reduction through systematic scan reconfiguration

Ahmad Al-Yamani; Narendra Devta-Prasanna; Erik Chmelar; Mikhail Grinchuk; Arun Gunda

doi:10.1109/TCAD.2007.8361584

Scan test cost and power reduction through systematic scan reconfiguration

Ahmad Al-Yamani
, Narendra Devta-Prasanna
, Erik Chmelar
, Mikhail Grinchuk
, Arun Gunda

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

Original language	English
Article number	8361584
Pages (from-to)	907-918
Number of pages	12
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	26
Issue number	5
DOIs	https://doi.org/10.1109/TCAD.2007.8361584
State	Published - May 2007

Bibliographical note

Publisher Copyright:
© 1982-2012 IEEE.

Keywords

Design for testability
integrated circuit testing
self-testing
test set compression

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/TCAD.2007.8361584

Cite this

@article{f52ee9bb6b064549a0aeaa3a0e1c3313,

title = "Scan test cost and power reduction through systematic scan reconfiguration",

abstract = "This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.",

keywords = "Design for testability, integrated circuit testing, self-testing, test set compression",

author = "Ahmad Al-Yamani and Narendra Devta-Prasanna and Erik Chmelar and Mikhail Grinchuk and Arun Gunda",

note = "Publisher Copyright: {\textcopyright} 1982-2012 IEEE.",

year = "2007",

month = may,

doi = "10.1109/TCAD.2007.8361584",

language = "English",

volume = "26",

pages = "907--918",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Scan test cost and power reduction through systematic scan reconfiguration

AU - Al-Yamani, Ahmad

AU - Devta-Prasanna, Narendra

AU - Chmelar, Erik

AU - Grinchuk, Mikhail

AU - Gunda, Arun

PY - 2007/5

Y1 - 2007/5

N2 - This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

AB - This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

KW - Design for testability

KW - integrated circuit testing

KW - self-testing

KW - test set compression

UR - https://www.scopus.com/pages/publications/85082044094

U2 - 10.1109/TCAD.2007.8361584

DO - 10.1109/TCAD.2007.8361584

M3 - Article

AN - SCOPUS:85082044094

SN - 0278-0070

VL - 26

SP - 907

EP - 918

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 5

M1 - 8361584

ER -

Scan test cost and power reduction through systematic scan reconfiguration

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this