Scan test cost and power reduction through systematic scan reconfiguration

Ahmad Al-Yamani; Narendra Devta-Prasanna; Erik Chmelar; Mikhail Grinchuk; Arun Gunda

doi:10.1109/TCAD.2006.884582

Scan test cost and power reduction through systematic scan reconfiguration

Ahmad Al-Yamani^*, Narendra Devta-Prasanna, Erik Chmelar, Mikhail Grinchuk, Arun Gunda

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power coasumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10 × to 40 × compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

Original language	English
Pages (from-to)	907-918
Number of pages	12
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	26
Issue number	5
DOIs	https://doi.org/10.1109/TCAD.2006.884582
State	Published - May 2007

Keywords

Design for testability
Integrated circuit testing
Self-testing
Test set compression

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2006.884582

Cite this

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title = "Scan test cost and power reduction through systematic scan reconfiguration",

abstract = "This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power coasumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10 × to 40 × compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.",

keywords = "Design for testability, Integrated circuit testing, Self-testing, Test set compression",

author = "Ahmad Al-Yamani and Narendra Devta-Prasanna and Erik Chmelar and Mikhail Grinchuk and Arun Gunda",

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AU - Al-Yamani, Ahmad

AU - Devta-Prasanna, Narendra

AU - Chmelar, Erik

AU - Grinchuk, Mikhail

AU - Gunda, Arun

PY - 2007/5

Y1 - 2007/5

N2 - This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power coasumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10 × to 40 × compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

AB - This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power coasumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10 × to 40 × compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

KW - Design for testability

KW - Integrated circuit testing

KW - Self-testing

KW - Test set compression

UR - https://www.scopus.com/pages/publications/34248592851

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JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 5

ER -

Scan test cost and power reduction through systematic scan reconfiguration

Abstract

Keywords

ASJC Scopus subject areas

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