Scalable FPGA implementation for mixed-norm LMS-LMF adaptive filters

Abdul Rahman Elshafei*, Azzedine Zerguine, Abdelhafid Bouhraoua

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work proposes a scalable architecture for implementing a mixed-norm LMS-LMF adaptive algorithm using a 16-bit fixedpoint arithmetic representation. The hardware scalability allows flexibility in the choice of selecting the order of the filter without redesigning the hardware. The filter also allows flexibility in using application specific sampling frequencies. The hardware architecture was implemented using a Virtex-4 FPGA ML402 board. A 2nd order prototype was tested through both hardware and software simulations. According to the synthesis and the simulation results obtained, the adaptive filter coefficients would converge in less than 17μs with accuracy greater than 95%.

Original languageEnglish
Title of host publicationProceedings of the 2009 ACM International Wireless Communications and Mobile Computing Conference, IWCMC 2009
PublisherAssociation for Computing Machinery (ACM)
Pages304-308
Number of pages5
ISBN (Print)9781605585697
DOIs
StatePublished - 2009

Publication series

NameProceedings of the 2009 ACM International Wireless Communications and Mobile Computing, Connecting the World Wirelessly, IWCMC 2009

Keywords

  • Adaptive filters
  • FPGA
  • LMS-LMF
  • Scalable architecture

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Software

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