Abstract
This paper investigates the impact of scalability on h-BN based memristors, with a focus on yield and variability. Motivated by the atomic-defect-enabled operation mechanism of h-BN memristors, a stochastic geometry modelling framework is employed to characterize the distribution of atomic defects across a large array of devices. This is coupled with a probabilistic defect activation model to characterize the SET voltage. The model is benchmarked to experimental results for monolayer and multi-layer h-BN devices. The presented results highlight the profound impact of scalability on device yield, device-to-device variability and SET voltage.
Original language | English |
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Title of host publication | 2023 Silicon Nanoelectronics Workshop, SNW 2023 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 109-110 |
Number of pages | 2 |
ISBN (Electronic) | 9784863488083 |
DOIs | |
State | Published - 2023 |
Event | 26th Silicon Nanoelectronics Workshop, SNW 2023 - Kyoto, Japan Duration: 11 Jun 2023 → 12 Jun 2023 |
Publication series
Name | 2023 Silicon Nanoelectronics Workshop, SNW 2023 |
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Conference
Conference | 26th Silicon Nanoelectronics Workshop, SNW 2023 |
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Country/Territory | Japan |
City | Kyoto |
Period | 11/06/23 → 12/06/23 |
Bibliographical note
Publisher Copyright:© 2023 JSAP.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Electronic, Optical and Magnetic Materials