Abstract
High level synthesis refers to the process of synthesizing the hardware of a digital system from a high level description. This paper presents an integrated system which accepts as input a purely behavioral description expressed in the ''bc'' language and transforms it into hardware (IC layout). The bc description is first transformed into a stack representation which is used to generate an optimized RTL description in the AHPL language. The AHPL description is finally synthesized into hardware.
| Original language | English |
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| Journal | ARABIAN JOURNAL FOR SCIENCE & ENGINEERING |
| State | Published - 1994 |