Robust two-phase RZ asynchronous SoC interconnects

Muhammad E.S. Elrabaa

doi:10.1109/TVLSI.2010.2042240

Robust two-phase RZ asynchronous SoC interconnects

Muhammad E.S. Elrabaa^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A novel two-phase RZ delay-insensitive asynchronous handshaking protocol for on-chip communication has been developed along with an efficient and robust dual-rail circuit implementation (Transmitter/Receiver). Performance was verified using SPICE simulations with a 0.13 μ m, 1.2 V technology and compared to that of the best-in-class asynchronous transceivers in terms of forward and backward latencies, throughput, energy per bit transfer and design complexity. Results demonstrate the superior overall performance of the new transceiver.

Original language	English
Article number	5422810
Pages (from-to)	1086-1089
Number of pages	4
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2010.2042240
State	Published - Jun 2011

Bibliographical note

Funding Information:
Manuscript received November 14, 2009; revised December 20, 2009. First published March 01, 2010; current version published May 25, 2011. This work was supported by King Fahd University of Petroleum and Minerals (KFUPM) Grant IN070367. The author is with the Computer Engineering Department, KFUPM, Dhahran 31261, Saudi Arabia (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2010.2042240

Keywords

Asynchronous interconnects
CMOS digital integrated circuits
networks-on-chip (NoC)
systems-on-chip (SoC)

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TVLSI.2010.2042240

Cite this

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abstract = "A novel two-phase RZ delay-insensitive asynchronous handshaking protocol for on-chip communication has been developed along with an efficient and robust dual-rail circuit implementation (Transmitter/Receiver). Performance was verified using SPICE simulations with a 0.13 μ m, 1.2 V technology and compared to that of the best-in-class asynchronous transceivers in terms of forward and backward latencies, throughput, energy per bit transfer and design complexity. Results demonstrate the superior overall performance of the new transceiver.",

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Robust two-phase RZ asynchronous SoC interconnects

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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