Reduced switch count-based N-level boost inverter topology for higher voltage gain

  • Marif Daula Siddique
  • , Bhimireddy Prathap Reddy
  • , Atif Iqbal
  • , Saad Mekhilef*
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

45 Scopus citations

Abstract

This study proposes a new boost inverter based on a switched-capacitor concept with reduced switch count. The basic unit is a five-level topology, which inherently generates the AC output voltage with the self-voltage balancing of the capacitors. A conventional carrier-based sinusoidal modulation technique has been designed to maintain the capacitor voltage up to the input source voltage. The N-level structure of the proposed basic unit is also presented, which has the additional advantage of higher voltage gain with a single input. A detailed comparison with other similar topologies has been carried out. A laboratory prototype has been used to test the workability of the proposed basic unit and its extension for seven-level through several results.

Original languageEnglish
Pages (from-to)3505-3509
Number of pages5
JournalIET Power Electronics
Volume13
Issue number15
DOIs
StatePublished - 25 Nov 2020

Bibliographical note

Publisher Copyright:
© 2020 Institution of Engineering and Technology. All rights reserved.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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