Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Recently, a shift from CMOS lithography to nanoelectronics chemical assembly has been under investigation. Nanoscale components are assembled into arrays of low-power and high-density nanofabrics, which can be integrated with conventional CMOS systems. The inability to achieve inexpensive defect-free mass manufacturing of nanoelectronics is the largest impediment of their adoption. Limited nanowire lengths and defect-prone nanodevices pose significant challenges for design automation tools. In this work, we propose a design phase for cell mapping and reconfiguration in novel hybrid CMOS/nanoelectronics architecture called CMOL. Reconfiguration consists of finding new suitable physical location for each gate such that the circuit becomes defect free. The novelty of this work is to engineer non-deterministic iterative search heuristics, namely simulated evolution (SimE) and Tabu search (TS), to find cell assignment around defective nano-components. Circuits of various sizes from ISCAS’89 benchmarks are used to evaluate the designed heuristics. Results show that SimE and TS yield successful reconfigurations in reasonable computation time when nanodevice defect rate is as high as 50 % and nanowire cut rate up to 70 %.