Recent advances in logic synthesis with testability

J. Rajski; J. Vasudevamurthy; A. El-Maleh

doi:10.1109/VTEST.1992.232761

Recent advances in logic synthesis with testability

J. Rajski, J. Vasudevamurthy, A. El-Maleh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

The primary consideration in the entire logic synthesis process is the quality of the resulting circuit measured by its speed, chip area, and recently also testability. The crucial phase in automatic logic synthesis, where all these parameters are determined, is the process of decomposition and factorization which generates multilevel Boolean equations for the synthesized circuit. There are a number of various aspects of testability. These aspects depend on the fault models and testing strategies used. One of the basic objectives is to synthesize circuits that are completely testable for a given class of faults.

Original language	English
Title of host publication	Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992
Publisher	IEEE Computer Society
Pages	254-256
Number of pages	3
ISBN (Electronic)	0780306236
DOIs	https://doi.org/10.1109/VTEST.1992.232761
State	Published - 1992
Externally published	Yes

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	1992-April

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/VTEST.1992.232761

Cite this

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title = "Recent advances in logic synthesis with testability",

abstract = "The primary consideration in the entire logic synthesis process is the quality of the resulting circuit measured by its speed, chip area, and recently also testability. The crucial phase in automatic logic synthesis, where all these parameters are determined, is the process of decomposition and factorization which generates multilevel Boolean equations for the synthesized circuit. There are a number of various aspects of testability. These aspects depend on the fault models and testing strategies used. One of the basic objectives is to synthesize circuits that are completely testable for a given class of faults.",

author = "J. Rajski and J. Vasudevamurthy and A. El-Maleh",

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year = "1992",

doi = "10.1109/VTEST.1992.232761",

language = "English",

series = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE Computer Society",

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Recent advances in logic synthesis with testability. / Rajski, J.; Vasudevamurthy, J.; El-Maleh, A.
Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992. IEEE Computer Society, 1992. p. 254-256 232761 (Proceedings of the IEEE VLSI Test Symposium; Vol. 1992-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Vasudevamurthy, J.

AU - El-Maleh, A.

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AB - The primary consideration in the entire logic synthesis process is the quality of the resulting circuit measured by its speed, chip area, and recently also testability. The crucial phase in automatic logic synthesis, where all these parameters are determined, is the process of decomposition and factorization which generates multilevel Boolean equations for the synthesized circuit. There are a number of various aspects of testability. These aspects depend on the fault models and testing strategies used. One of the basic objectives is to synthesize circuits that are completely testable for a given class of faults.

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BT - Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992

PB - IEEE Computer Society

ER -

Recent advances in logic synthesis with testability

Abstract

Publication series

Bibliographical note

ASJC Scopus subject areas

Access to Document

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Cite this