Prelayout timing analysis of cell-based VLSI designs

With the advances in VLSI design, chip timing is becoming dominated by interconnect delays rather than macro performances. For many existing large computer circuits, the interconnect delays already account for more than one-half of the clock cycle, and the portion of propagation time in the cycle continues to grow. Optimized for timing, the design can permit a 25-35% increase in the clock rate without any changes in the logic or cell design. This fact requires a change in the approach to timing problems throughout the design process. This need is clearly understood by designers of supercomputers and many types of fast-clock electronics. The evaluation and prediction of timing performance of a VLSI design is traditionally based on the identification and evaluation of the critical paths. The paper demonstrates that existing methodologies of identification of the critical paths are deficient because they do not take into consideration many important characteristics of the design which influence performance. New criteria and a new methodology are proposed for the prediction of the critical paths prior to the physical design step, and the application of this methodology to real designs is demonstrated.