PR-PUF: A Reconfigurable Strong RRAM PUF

Gokulnath Rajendran; Furqan Zahoor; Simranjeet Singh; Farhad Merchant; Vikas Rana; Anupam Chattopadhyay

doi:10.1109/VLSI-SoC57769.2023.10321884

PR-PUF: A Reconfigurable Strong RRAM PUF

Gokulnath Rajendran^*
, Furqan Zahoor^*
, Simranjeet Singh
, Farhad Merchant
, Vikas Rana
, Anupam Chattopadhyay^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Physical Unclonable Functions (PUFs) offer the natural advantage of built-in key generation, thus eliminating the costly process of embedding unique key after manufacturing millions of integrated circuits. When PUFs are deployed for the application, all the Challenge-Response Pairs (CRP) are collected and stored in a trusted server, and the responses are compared with the one from the device during the run-time - forming the crux of various security protocols. Two issues are commonly faced during PUF designs. First, to enhance the applicability of PUF, larger set of CRP is desirable, which is referred to as a strong PUF. Second, due to the emergence of machine learning-based PUF modelling attacks, it is now imperative to have a PUF demonstrating resistance against such attacks. In this paper, we propose a novel Parity Resistive RAM PUF (PR-PUF) implemented using RRAM crossbar architecture. PR-PUF supports low-overhead reconfiguration, where both the original and reconfigured CRP space enhances the CRP size, with average uniqueness between reconfiguration of 49.98%. The construction also demonstrates excellent robustness against various modeling attacks. We present detailed design analysis and circuit-level simulation studies.

Original language	English
Title of host publication	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
Publisher	IEEE Computer Society
ISBN (Electronic)	9798350325997
DOIs	https://doi.org/10.1109/VLSI-SoC57769.2023.10321884
State	Published - 2023
Externally published	Yes
Event	31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 - Dubai, United Arab Emirates Duration: 16 Oct 2023 → 18 Oct 2023

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023
Country/Territory	United Arab Emirates
City	Dubai
Period	16/10/23 → 18/10/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Keywords

PUF
RRAM
Security

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC57769.2023.10321884

Cite this

Rajendran, G., Zahoor, F., Singh, S., Merchant, F., Rana, V., & Chattopadhyay, A. (2023). PR-PUF: A Reconfigurable Strong RRAM PUF. In 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC57769.2023.10321884

@inproceedings{3117253b06994bedb948cbf2845764c7,

title = "PR-PUF: A Reconfigurable Strong RRAM PUF",

abstract = "Physical Unclonable Functions (PUFs) offer the natural advantage of built-in key generation, thus eliminating the costly process of embedding unique key after manufacturing millions of integrated circuits. When PUFs are deployed for the application, all the Challenge-Response Pairs (CRP) are collected and stored in a trusted server, and the responses are compared with the one from the device during the run-time - forming the crux of various security protocols. Two issues are commonly faced during PUF designs. First, to enhance the applicability of PUF, larger set of CRP is desirable, which is referred to as a strong PUF. Second, due to the emergence of machine learning-based PUF modelling attacks, it is now imperative to have a PUF demonstrating resistance against such attacks. In this paper, we propose a novel Parity Resistive RAM PUF (PR-PUF) implemented using RRAM crossbar architecture. PR-PUF supports low-overhead reconfiguration, where both the original and reconfigured CRP space enhances the CRP size, with average uniqueness between reconfiguration of 49.98\%. The construction also demonstrates excellent robustness against various modeling attacks. We present detailed design analysis and circuit-level simulation studies.",

keywords = "PUF, RRAM, Security",

author = "Gokulnath Rajendran and Furqan Zahoor and Simranjeet Singh and Farhad Merchant and Vikas Rana and Anupam Chattopadhyay",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 ; Conference date: 16-10-2023 Through 18-10-2023",

year = "2023",

doi = "10.1109/VLSI-SoC57769.2023.10321884",

language = "English",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

publisher = "IEEE Computer Society",

booktitle = "2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023",

address = "United States",

}

Rajendran, G, Zahoor, F, Singh, S, Merchant, F, Rana, V & Chattopadhyay, A 2023, PR-PUF: A Reconfigurable Strong RRAM PUF. in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, 16/10/23. https://doi.org/10.1109/VLSI-SoC57769.2023.10321884

PR-PUF: A Reconfigurable Strong RRAM PUF. / Rajendran, Gokulnath; Zahoor, Furqan; Singh, Simranjeet et al.
2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. IEEE Computer Society, 2023. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - PR-PUF

T2 - 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023

AU - Rajendran, Gokulnath

AU - Zahoor, Furqan

AU - Singh, Simranjeet

AU - Merchant, Farhad

AU - Rana, Vikas

AU - Chattopadhyay, Anupam

PY - 2023

Y1 - 2023

N2 - Physical Unclonable Functions (PUFs) offer the natural advantage of built-in key generation, thus eliminating the costly process of embedding unique key after manufacturing millions of integrated circuits. When PUFs are deployed for the application, all the Challenge-Response Pairs (CRP) are collected and stored in a trusted server, and the responses are compared with the one from the device during the run-time - forming the crux of various security protocols. Two issues are commonly faced during PUF designs. First, to enhance the applicability of PUF, larger set of CRP is desirable, which is referred to as a strong PUF. Second, due to the emergence of machine learning-based PUF modelling attacks, it is now imperative to have a PUF demonstrating resistance against such attacks. In this paper, we propose a novel Parity Resistive RAM PUF (PR-PUF) implemented using RRAM crossbar architecture. PR-PUF supports low-overhead reconfiguration, where both the original and reconfigured CRP space enhances the CRP size, with average uniqueness between reconfiguration of 49.98%. The construction also demonstrates excellent robustness against various modeling attacks. We present detailed design analysis and circuit-level simulation studies.

AB - Physical Unclonable Functions (PUFs) offer the natural advantage of built-in key generation, thus eliminating the costly process of embedding unique key after manufacturing millions of integrated circuits. When PUFs are deployed for the application, all the Challenge-Response Pairs (CRP) are collected and stored in a trusted server, and the responses are compared with the one from the device during the run-time - forming the crux of various security protocols. Two issues are commonly faced during PUF designs. First, to enhance the applicability of PUF, larger set of CRP is desirable, which is referred to as a strong PUF. Second, due to the emergence of machine learning-based PUF modelling attacks, it is now imperative to have a PUF demonstrating resistance against such attacks. In this paper, we propose a novel Parity Resistive RAM PUF (PR-PUF) implemented using RRAM crossbar architecture. PR-PUF supports low-overhead reconfiguration, where both the original and reconfigured CRP space enhances the CRP size, with average uniqueness between reconfiguration of 49.98%. The construction also demonstrates excellent robustness against various modeling attacks. We present detailed design analysis and circuit-level simulation studies.

KW - PUF

KW - RRAM

KW - Security

UR - https://www.scopus.com/pages/publications/85179837279

U2 - 10.1109/VLSI-SoC57769.2023.10321884

DO - 10.1109/VLSI-SoC57769.2023.10321884

M3 - Conference contribution

AN - SCOPUS:85179837279

T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

BT - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023

PB - IEEE Computer Society

Y2 - 16 October 2023 through 18 October 2023

ER -

PR-PUF: A Reconfigurable Strong RRAM PUF

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this