TY - JOUR
T1 - Performance driven standard-cell placement using the genetic algorithm
AU - Youssef, Habib
AU - Sait, Sadiq M.
AU - Nassar, Khaled
AU - Benten, Muhammad S.T.
PY - 1995
Y1 - 1995
N2 - Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of α-criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20%.
AB - Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of α-criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20%.
UR - https://www.scopus.com/pages/publications/0029213244
U2 - 10.1109/glsv.1995.516037
DO - 10.1109/glsv.1995.516037
M3 - Conference article
AN - SCOPUS:0029213244
SN - 1066-1395
SP - 124
EP - 127
JO - Proceedings of the IEEE Great Lakes Symposium on VLSI
JF - Proceedings of the IEEE Great Lakes Symposium on VLSI
ER -