Optimization of digital BiCMOS circuits, an overview

M. S. Elrabaa; M. I. Elmasry

doi:10.1109/MWSCAS.1992.271259

Optimization of digital BiCMOS circuits, an overview

M. S. Elrabaa
, M. I. Elmasry

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An overview of the optimization of buffer chains and multilevel logic in a BiC-MOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS CML circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized.

Original language	English
Title of host publication	1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	571-574
Number of pages	4
ISBN (Electronic)	0780305108
DOIs	https://doi.org/10.1109/MWSCAS.1992.271259
State	Published - 1992
Externally published	Yes

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	1992-August
ISSN (Print)	1548-3746

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.1992.271259

Cite this

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title = "Optimization of digital BiCMOS circuits, an overview",

abstract = "An overview of the optimization of buffer chains and multilevel logic in a BiC-MOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS CML circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized.",

author = "Elrabaa, \{M. S.\} and Elmasry, \{M. I.\}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.",

year = "1992",

doi = "10.1109/MWSCAS.1992.271259",

language = "English",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "571--574",

booktitle = "1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems",

address = "United States",

}

Optimization of digital BiCMOS circuits, an overview. / Elrabaa, M. S.; Elmasry, M. I.
1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 1992. p. 571-574 271259 (Midwest Symposium on Circuits and Systems; Vol. 1992-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Elrabaa, M. S.

AU - Elmasry, M. I.

PY - 1992

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N2 - An overview of the optimization of buffer chains and multilevel logic in a BiC-MOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS CML circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized.

AB - An overview of the optimization of buffer chains and multilevel logic in a BiC-MOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS CML circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized.

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U2 - 10.1109/MWSCAS.1992.271259

DO - 10.1109/MWSCAS.1992.271259

M3 - Conference contribution

AN - SCOPUS:85065732490

T3 - Midwest Symposium on Circuits and Systems

SP - 571

EP - 574

BT - 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Optimization of digital BiCMOS circuits, an overview

Abstract

Publication series

Bibliographical note

ASJC Scopus subject areas

Access to Document

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Cite this