On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs

Unreliable and harsh environmental conditions in avionics and space applications demand run-time adaptation capabilities to withstand environmental changes and radiation-induced faults. Modern SRAM-based FPGAs integrating high computational power with partial and dynamic reconfiguration abilities are a usual candidate for such systems. However, due to the vulnerability of these devices to Single Event Upsets (SEUs), designs need proper fault-handling mechanisms. In this work we propose a novel circuit instrumentation method for probing Triple Modular Redundancy (TMR) circuits for error detection at the granularity of individual domains and then use selective run-time dynamic reconfiguration for recovery. Error detection logic is inserted in the physical net-list to identify and localize faults. Moreover, selective domain reconfiguration is achieved by careful considerations in the placement phase on the FPGA reconfigurable area. The proposed technique is suitable for systems having hard real-time constraints. Our results demonstrate that this approach has an overhead of 2 LUTs per majority voter in internal partitions in terms of area when compared to the standard TMR circuits. In addition, it brings down the reconfiguration times of TMR circuits to a single domain and ensures a 100% availability of the device assuming the Single Event Upset fault model.