On improving the critical path delay of PathFinder at smaller channel widths

Umair F. Siddiqi; Sadiq M. Sait

doi:10.1109/ISCIT57293.2023.10376068

On improving the critical path delay of PathFinder at smaller channel widths

Umair F. Siddiqi^*
, Sadiq M. Sait

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

PathFinder, a popular FPGA routing tool, employs negotiated congestion routing that reduces the congestion by forcing the nets to detour through uncongested interconnects. However, such detouring often gives less importance to the delay of the interconnects and more to their congestion. This approach may increase the critical path delay (CPD) under tight capacity constraints. In this work, we propose a historical cost function for the negotiated congestion routing that ensures solutions have small CPD values. The proposed historical cost function is integrated into the latest version of PathFinder, and its performance is evaluated using Titan23 FPGA benchmarks. The results indicate that the proposed cost function can enable PathFinder to converge to solutions of smaller CPD, even for small channel widths. Statistical tests are employed to verify the significance of the benefits of the proposed approach.

Original language	English
Title of host publication	22nd International Symposium on Communications and Information Technologies, ISCIT 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	127-132
Number of pages	6
ISBN (Electronic)	9781665457316
DOIs	https://doi.org/10.1109/ISCIT57293.2023.10376068
State	Published - 2023
Event	22nd International Symposium on Communications and Information Technologies, ISCIT 2023 - Sydney, Australia Duration: 16 Oct 2023 → 18 Oct 2023

Publication series

Name	22nd International Symposium on Communications and Information Technologies, ISCIT 2023

Conference

Conference	22nd International Symposium on Communications and Information Technologies, ISCIT 2023
Country/Territory	Australia
City	Sydney
Period	16/10/23 → 18/10/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

FPGA
electronic design automation
intelligent manufacturing
negotiated congestion
routing

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Signal Processing
Instrumentation
Acoustics and Ultrasonics
Information Systems

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCIT57293.2023.10376068

Cite this

Siddiqi, U. F., & Sait, S. M. (2023). On improving the critical path delay of PathFinder at smaller channel widths. In 22nd International Symposium on Communications and Information Technologies, ISCIT 2023 (pp. 127-132). (22nd International Symposium on Communications and Information Technologies, ISCIT 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCIT57293.2023.10376068

@inproceedings{89a11bce279742b9a1106cfcb3ccb640,

title = "On improving the critical path delay of PathFinder at smaller channel widths",

abstract = "PathFinder, a popular FPGA routing tool, employs negotiated congestion routing that reduces the congestion by forcing the nets to detour through uncongested interconnects. However, such detouring often gives less importance to the delay of the interconnects and more to their congestion. This approach may increase the critical path delay (CPD) under tight capacity constraints. In this work, we propose a historical cost function for the negotiated congestion routing that ensures solutions have small CPD values. The proposed historical cost function is integrated into the latest version of PathFinder, and its performance is evaluated using Titan23 FPGA benchmarks. The results indicate that the proposed cost function can enable PathFinder to converge to solutions of smaller CPD, even for small channel widths. Statistical tests are employed to verify the significance of the benefits of the proposed approach.",

keywords = "FPGA, electronic design automation, intelligent manufacturing, negotiated congestion, routing",

author = "Siddiqi, \{Umair F.\} and Sait, \{Sadiq M.\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 22nd International Symposium on Communications and Information Technologies, ISCIT 2023 ; Conference date: 16-10-2023 Through 18-10-2023",

year = "2023",

doi = "10.1109/ISCIT57293.2023.10376068",

language = "English",

series = "22nd International Symposium on Communications and Information Technologies, ISCIT 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "127--132",

booktitle = "22nd International Symposium on Communications and Information Technologies, ISCIT 2023",

address = "United States",

}

Siddiqi, UF & Sait, SM 2023, On improving the critical path delay of PathFinder at smaller channel widths. in 22nd International Symposium on Communications and Information Technologies, ISCIT 2023. 22nd International Symposium on Communications and Information Technologies, ISCIT 2023, Institute of Electrical and Electronics Engineers Inc., pp. 127-132, 22nd International Symposium on Communications and Information Technologies, ISCIT 2023, Sydney, Australia, 16/10/23. https://doi.org/10.1109/ISCIT57293.2023.10376068

On improving the critical path delay of PathFinder at smaller channel widths. / Siddiqi, Umair F.; Sait, Sadiq M.
22nd International Symposium on Communications and Information Technologies, ISCIT 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 127-132 (22nd International Symposium on Communications and Information Technologies, ISCIT 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - On improving the critical path delay of PathFinder at smaller channel widths

AU - Siddiqi, Umair F.

AU - Sait, Sadiq M.

PY - 2023

Y1 - 2023

N2 - PathFinder, a popular FPGA routing tool, employs negotiated congestion routing that reduces the congestion by forcing the nets to detour through uncongested interconnects. However, such detouring often gives less importance to the delay of the interconnects and more to their congestion. This approach may increase the critical path delay (CPD) under tight capacity constraints. In this work, we propose a historical cost function for the negotiated congestion routing that ensures solutions have small CPD values. The proposed historical cost function is integrated into the latest version of PathFinder, and its performance is evaluated using Titan23 FPGA benchmarks. The results indicate that the proposed cost function can enable PathFinder to converge to solutions of smaller CPD, even for small channel widths. Statistical tests are employed to verify the significance of the benefits of the proposed approach.

AB - PathFinder, a popular FPGA routing tool, employs negotiated congestion routing that reduces the congestion by forcing the nets to detour through uncongested interconnects. However, such detouring often gives less importance to the delay of the interconnects and more to their congestion. This approach may increase the critical path delay (CPD) under tight capacity constraints. In this work, we propose a historical cost function for the negotiated congestion routing that ensures solutions have small CPD values. The proposed historical cost function is integrated into the latest version of PathFinder, and its performance is evaluated using Titan23 FPGA benchmarks. The results indicate that the proposed cost function can enable PathFinder to converge to solutions of smaller CPD, even for small channel widths. Statistical tests are employed to verify the significance of the benefits of the proposed approach.

KW - FPGA

KW - electronic design automation

KW - intelligent manufacturing

KW - negotiated congestion

KW - routing

UR - https://www.scopus.com/pages/publications/85183457000

U2 - 10.1109/ISCIT57293.2023.10376068

DO - 10.1109/ISCIT57293.2023.10376068

M3 - Conference contribution

AN - SCOPUS:85183457000

T3 - 22nd International Symposium on Communications and Information Technologies, ISCIT 2023

SP - 127

EP - 132

BT - 22nd International Symposium on Communications and Information Technologies, ISCIT 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 22nd International Symposium on Communications and Information Technologies, ISCIT 2023

Y2 - 16 October 2023 through 18 October 2023

ER -

Siddiqi UF, Sait SM. On improving the critical path delay of PathFinder at smaller channel widths. In 22nd International Symposium on Communications and Information Technologies, ISCIT 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 127-132. (22nd International Symposium on Communications and Information Technologies, ISCIT 2023). doi: 10.1109/ISCIT57293.2023.10376068

On improving the critical path delay of PathFinder at smaller channel widths

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

Fingerprint

Cite this