New hardware protocol architecture for computer networks

In the past decades, the conventional multi-layer protocols implemented in software were fast enough to match the speed of the lines which were measured in Kilobits per second. Nowadays, due to the development of fiber optics and copper wire technologies, line speeds are measured in Gigabits per second. However, the advantages of high-speed technologies are lost in the large processing overhead of the high-level protocols, leading to a large delay and low throughput. The potential of hardware implementation has influenced the design of the communication networks. Hence, we propose a hardware implementation of the transport protocol layer for the OSI model. It is probably easier and cheaper today, with the advances in VLSI, to implement a large and fast communications protocol as hardware on a single silicon chip rather than in software. The main objective is to prove that the hardware implementation is logically feasible. The study concentrates on the queuing system that controls the data flow between the two end users. This includes detecting duplicate, lost, and mis-sequenced data. The study also includes hardware complexity estimation of the proposed architecture.