Abstract
The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(√n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF).
Original language | English |
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Pages (from-to) | 987-1000 |
Number of pages | 14 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 16 |
Issue number | 9 |
DOIs | |
State | Published - 1997 |
Bibliographical note
Funding Information:Manuscript received January 6, 1995; revised April 9, 1997. This work was supported by KFUPM. This paper was recommended by Associate Editor W. Maly. A. A. Amin and M. Y. Osman are with the Department of Computer Engineering, King Fahd University of Petroleum & Minerals, Dhahran 31261, Saudi Arabia. R. E. Abdel-Aal is with the Energy Research Laboratory, Research Institute, King Fahd University of Petroleum & Minerals, Dhahran 31261, Saudi Arabia. H. Al-Muhtaseb is with the Department of Information and Computer Science, King Fahd University of Petroleum & Minerals, Dhahran 31261, Saudi Arabia. Publisher Item Identifier S 0278-0070(97)09007-6.
Keywords
- Address decoder faults
- Built-in self-test (bist)
- Cross-port decoder faults
- Design for testability
- Duplex dynamic neighborhood pattern-sensitive faults
ASJC Scopus subject areas
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering