Multiple-Input Floating-Point Adders: A Comprehensive Review

Floating-point addition is pivotal in various computational applications, including scientific computing, machine learning, and graphics processing. Traditional two-input floating-point adders (FPADD2) are widely used but become bottlenecks in scenarios requiring efficient multi-operand summation. The growing demand for high-performance computing has spurred interest in multiple-input floating-point adders (FPADDn), which simultaneously handle multiple operands to enhance throughput and reduce latency. This paper provides a comprehensive review of FPADDn architectures, exploring key design principles, implementation techniques, and challenges such as precision, hardware complexity, and rounding errors. Modern approaches leveraging hierarchical tree structures, parallelism, and pipelining are discussed, highlighting their advantages and trade-offs.