Multiple hash matching units (MHMU): An algorithmic ternary content addressable memory design for field programmable gate arrays

  • Pedro Reviriego
  • , Salvatore Pontarelli
  • , Anees Ullah
  • , Ali Zahir
  • , Giuseppe Bianchi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

As applications and user requirements are constantly evolving, there is a need to provide flexible networks that are able to process packets at high speed. One of the basic functions used for packet processing is matching a key formed by some fields of the incoming packet header against a set of stored rules. This is done for example to determine the next hop of a packet or to apply security checks on a firewall. In many cases, the stored rules have do not care bits as that enables a more flexible and compact representation of the rules. Therefore, the matching can be done in hardware using Ternary Content Addressable Memories (TCAMs). However, TCAMs pose several problems in many implementations. For example, for ASICs they require much more circuit area and power than standard SRAMs. On the other hand, designs based on programmable logic such as Field Programmable Gate Arrays (FPGAs) can only use the blocks provided by the FPGA that do not typically include TCAMs. In this last case, a TCAM can be emulated using the FPGA logic resources but with a large cost. To reduce the cost of implementing TCAMs, a number of algorithmic solutions have been proposed and are known as Algorithmic TCAMs or A-TCAMs. Most of those schemes target either software or ASIC implementations. In this paper we present Multiple Hash Matching Units (MHMU) an A-TCAM solution targeted towards FPGA implementations. The proposed scheme exploits the massive parallelism of FPGAs to implement many hash based matching units that use the embedded block RAM memories of the FPGA. The proposed MHMU scheme has been mapped to a Xilinx series 7 FPGA to check its efficiency in terms of resource usage and its scalability. To validate the effectiveness of MHMU, a simple configuration has been tested with Classbench generated sets of rules. The results show that the MHMU is able to consistently accommodate sets with several tens of thousands of rules with large keys.

Original languageEnglish
Title of host publication2018 IEEE 19th International Conference on High Performance Switching and Routing, HPSR 2018
PublisherIEEE Computer Society
ISBN (Electronic)9781538678015
DOIs
StatePublished - Jun 2018
Externally publishedYes
Event19th IEEE International Conference on High Performance Switching and Routing, HPSR 2018 - Bucharest, Romania
Duration: 18 Jun 201820 Jun 2018

Publication series

NameIEEE International Conference on High Performance Switching and Routing, HPSR
Volume2018-June
ISSN (Print)2325-5595
ISSN (Electronic)2325-5609

Conference

Conference19th IEEE International Conference on High Performance Switching and Routing, HPSR 2018
Country/TerritoryRomania
CityBucharest
Period18/06/1820/06/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

  • A-TCAM
  • FPGA
  • Packet Classification
  • TCAM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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