Multi-FPGA distributed MLP NN model for data reduction in the ePIC dRICH readout system

The dual-radiator RICH (dRICH) detector will use silicon photomultipliers (SiPMs) to detect Cherenkov radiation with single-photon sensitivity over an area of ∼3 m². It will be one of the main components for particle identification in the ePIC experiment at the EIC. With ∼320k detector channels, data will be read out through 4,992 Front End Boards (FEBs). Each of the 1,248 Readout Boards (RDOs) will aggregate data from four FEBs, and transmit it via a VTRx+ optical link to a 48-port Data Aggregation and Manipulation (DAM) board. Each module composed by one RDO and four FEBs is called Photo Detection Unit (PDU). The DAM boards will be implemented using the FPGA-based FELIX-155 cards developed for the Phase-II upgrade of the ATLAS experiment. Each board will merge and collect data from 42 RDOs, forwarding it to the ePIC data buffering system (Echelon 0) through a 100 GbE channel. The dRICH is partitioned into six sectors, and the readout of channels from each sector is performed by five DAMs, for a total of 30 boards for the whole detector. The SiPM Dark Count Rate (DCR) is expected to increase with the integrated luminosity during the experiment's lifetime, potentially leading to an excessive bandwidth demand on the DAQ system. To mitigate this risk, we designed a real-time data reduction system that will lower the detector output bandwidth by roughly an order of magnitude. This solution involves the implementation of a distributed data-flow processing architecture on the DAMs and on an additional FELIX-155 card that will act as a Trigger Processor (TP), which will selectively filter out events exclusively caused by DCR noise. The current design features a distributed Multi-Layer Perceptron (MLP) Neural Network trained for noise-only event discrimination. The model is composed of 30 separate MLP sub-network replicas, deployed one per DAM: each replica processes the local event information — coming from 42 adjacent PDUs — to extract a set of features that are passed to the TP using a direct low-latency communication channel. The TP firmware is composed of six sector-MLP sub-networks that, taking as input the merged features extracted by each of the five DAMs of a single sector, implement a further feature-extraction step for each sector. These produce the input for a final, single MLP layer that performs the classification task and generates the corresponding trigger signal to accept or discard the event depending on whether a physics (including background) signal is present alongside the DCR noise, or if only DCR noise is detected. The data reduction process will be synchronized with the main EIC clock running at 100 MHz, corresponding to ∼10 ns between electron-ion bunch crossings, presenting a significant challenge for its implementation in the dRICH DAQ system. We will outline our approach to addressing this issue and the overall system design, starting from dataset generation for the training and validation of the distributed NN model, covering FPGA computing pipelines and communication, up to the current status of the implementation and testbed results.