Abstract
Verification, Validation and Testing (VV&T) is an imperative procedure for life cycle analysis of safety critical embedded real-time (ERT) systems. It covers software engineering to system engineering with VV&T procedures for every stage of system design e.g. static testing, functional testing, unit testing, fault injection testing, consistency techniques, Software-In-The-Loop (SIL) testing, evolutionary testing, Hardware-In-The-Loop (HIL) testing, black box testing, white box testing, integration testing, system testing, system integration testing, etc. This chapter discusses some of the approaches to demonstrate the importance of model-based VV&T in safety critical embedded real-time system development. An industrial case study is used to demonstrate the implementation feasibility of the VV&T methods.
| Original language | English |
|---|---|
| Title of host publication | Embedded and Real Time System Development |
| Subtitle of host publication | A Software Engineering Perspective: Concepts, Methods and Principles |
| Publisher | Springer Verlag |
| Pages | 153-183 |
| Number of pages | 31 |
| ISBN (Print) | 9783642408878 |
| DOIs | |
| State | Published - 2014 |
| Externally published | Yes |
Publication series
| Name | Studies in Computational Intelligence |
|---|---|
| Volume | 520 |
| ISSN (Print) | 1860-949X |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 12 Responsible Consumption and Production
ASJC Scopus subject areas
- Artificial Intelligence
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