Model-based verification and validation of safety-critical embedded real-time systems: Formation and tools

Arsalan H. Khan*, Zeashan H. Khan, Zhang Weiguo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

11 Scopus citations

Abstract

Verification, Validation and Testing (VV&T) is an imperative procedure for life cycle analysis of safety critical embedded real-time (ERT) systems. It covers software engineering to system engineering with VV&T procedures for every stage of system design e.g. static testing, functional testing, unit testing, fault injection testing, consistency techniques, Software-In-The-Loop (SIL) testing, evolutionary testing, Hardware-In-The-Loop (HIL) testing, black box testing, white box testing, integration testing, system testing, system integration testing, etc. This chapter discusses some of the approaches to demonstrate the importance of model-based VV&T in safety critical embedded real-time system development. An industrial case study is used to demonstrate the implementation feasibility of the VV&T methods.

Original languageEnglish
Title of host publicationEmbedded and Real Time System Development
Subtitle of host publicationA Software Engineering Perspective: Concepts, Methods and Principles
PublisherSpringer Verlag
Pages153-183
Number of pages31
ISBN (Print)9783642408878
DOIs
StatePublished - 2014
Externally publishedYes

Publication series

NameStudies in Computational Intelligence
Volume520
ISSN (Print)1860-949X

ASJC Scopus subject areas

  • Artificial Intelligence

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