Minimizing test frequencies for linear analog circuits: New models and efficient solution methods

Mohand Bentobache; Ahcène Bounceur; Reinhardt Euler; Salvador Mir; Yann Kieffer

doi:10.1007/978-3-319-23799-2_9

Minimizing test frequencies for linear analog circuits: New models and efficient solution methods

Mohand Bentobache^*, Ahcène Bounceur, Reinhardt Euler, Salvador Mir, Yann Kieffer

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work presents new approaches to minimize the number of test frequencies for linear analog circuits. The cases of single and multiple fault detection regions for multiple test measures are considered. We first address the case when the injected faults have a single detection region in the frequency band. We show that the problem can be formulated as a set covering problem with a matrix having the consecutive-ones property for which the network simplex algorithm turns out to be very efficient. A second approach consists in modeling the problem by means of an interval graph, leading to its solution with a specific polynomialtime algorithm. A case-study of a biquadratic filter is presented for illustration purposes. Numerical simulations demonstrate that the two different approaches solve the optimization problem very fast. Finally, the optimization problems arising from multiple detection regions are modeled and solution approaches are discussed.

Original language	English
Title of host publication	VLSI-SoC
Subtitle of host publication	At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Revised and Extended Selected Papers
Editors	H. Fatih Ugurdag, Alex Orailoglu, Martin Margala, Luís Miguel Silveira, Ricardo Reis
Publisher	Springer New York LLC
Pages	188-207
Number of pages	20
ISBN (Print)	9783319237985
DOIs	https://doi.org/10.1007/978-3-319-23799-2_9
State	Published - 2015
Externally published	Yes
Event	21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey Duration: 6 Oct 2013 → 9 Oct 2013

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	461
ISSN (Print)	1868-4238

Conference

Conference	21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013
Country/Territory	Turkey
City	Istanbul
Period	6/10/13 → 9/10/13

Bibliographical note

Publisher Copyright:
© IFIP International Federation for Information Processing 2015.

Keywords

Analog circuit testing
Consecutive-ones property
Interval graphs
Linear programming
Set covering problem

ASJC Scopus subject areas

Information Systems and Management

Access to Document

10.1007/978-3-319-23799-2_9

Cite this

Bentobache, M., Bounceur, A., Euler, R., Mir, S., & Kieffer, Y. (2015). Minimizing test frequencies for linear analog circuits: New models and efficient solution methods. In H. F. Ugurdag, A. Orailoglu, M. Margala, L. M. Silveira, & R. Reis (Eds.), VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Revised and Extended Selected Papers (pp. 188-207). (IFIP Advances in Information and Communication Technology; Vol. 461). Springer New York LLC. https://doi.org/10.1007/978-3-319-23799-2_9

Bentobache, Mohand ; Bounceur, Ahcène ; Euler, Reinhardt et al. / Minimizing test frequencies for linear analog circuits : New models and efficient solution methods. VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Revised and Extended Selected Papers. editor / H. Fatih Ugurdag ; Alex Orailoglu ; Martin Margala ; Luís Miguel Silveira ; Ricardo Reis. Springer New York LLC, 2015. pp. 188-207 (IFIP Advances in Information and Communication Technology).

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title = "Minimizing test frequencies for linear analog circuits: New models and efficient solution methods",

abstract = "This work presents new approaches to minimize the number of test frequencies for linear analog circuits. The cases of single and multiple fault detection regions for multiple test measures are considered. We first address the case when the injected faults have a single detection region in the frequency band. We show that the problem can be formulated as a set covering problem with a matrix having the consecutive-ones property for which the network simplex algorithm turns out to be very efficient. A second approach consists in modeling the problem by means of an interval graph, leading to its solution with a specific polynomialtime algorithm. A case-study of a biquadratic filter is presented for illustration purposes. Numerical simulations demonstrate that the two different approaches solve the optimization problem very fast. Finally, the optimization problems arising from multiple detection regions are modeled and solution approaches are discussed.",

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author = "Mohand Bentobache and Ahc{\`e}ne Bounceur and Reinhardt Euler and Salvador Mir and Yann Kieffer",

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doi = "10.1007/978-3-319-23799-2_9",

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Bentobache, M, Bounceur, A, Euler, R, Mir, S & Kieffer, Y 2015, Minimizing test frequencies for linear analog circuits: New models and efficient solution methods. in HF Ugurdag, A Orailoglu, M Margala, LM Silveira & R Reis (eds), VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology, vol. 461, Springer New York LLC, pp. 188-207, 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, 6/10/13. https://doi.org/10.1007/978-3-319-23799-2_9

Minimizing test frequencies for linear analog circuits: New models and efficient solution methods. / Bentobache, Mohand; Bounceur, Ahcène; Euler, Reinhardt et al.
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Revised and Extended Selected Papers. ed. / H. Fatih Ugurdag; Alex Orailoglu; Martin Margala; Luís Miguel Silveira; Ricardo Reis. Springer New York LLC, 2015. p. 188-207 (IFIP Advances in Information and Communication Technology; Vol. 461).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Bentobache, Mohand

AU - Bounceur, Ahcène

AU - Euler, Reinhardt

AU - Mir, Salvador

AU - Kieffer, Yann

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PY - 2015

Y1 - 2015

N2 - This work presents new approaches to minimize the number of test frequencies for linear analog circuits. The cases of single and multiple fault detection regions for multiple test measures are considered. We first address the case when the injected faults have a single detection region in the frequency band. We show that the problem can be formulated as a set covering problem with a matrix having the consecutive-ones property for which the network simplex algorithm turns out to be very efficient. A second approach consists in modeling the problem by means of an interval graph, leading to its solution with a specific polynomialtime algorithm. A case-study of a biquadratic filter is presented for illustration purposes. Numerical simulations demonstrate that the two different approaches solve the optimization problem very fast. Finally, the optimization problems arising from multiple detection regions are modeled and solution approaches are discussed.

AB - This work presents new approaches to minimize the number of test frequencies for linear analog circuits. The cases of single and multiple fault detection regions for multiple test measures are considered. We first address the case when the injected faults have a single detection region in the frequency band. We show that the problem can be formulated as a set covering problem with a matrix having the consecutive-ones property for which the network simplex algorithm turns out to be very efficient. A second approach consists in modeling the problem by means of an interval graph, leading to its solution with a specific polynomialtime algorithm. A case-study of a biquadratic filter is presented for illustration purposes. Numerical simulations demonstrate that the two different approaches solve the optimization problem very fast. Finally, the optimization problems arising from multiple detection regions are modeled and solution approaches are discussed.

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Bentobache M, Bounceur A, Euler R, Mir S, Kieffer Y. Minimizing test frequencies for linear analog circuits: New models and efficient solution methods. In Ugurdag HF, Orailoglu A, Margala M, Silveira LM, Reis R, editors, VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Revised and Extended Selected Papers. Springer New York LLC. 2015. p. 188-207. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-319-23799-2_9

Minimizing test frequencies for linear analog circuits: New models and efficient solution methods

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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