Minimization of functional tests by statistical modelling of analogue circuits

Nourredine Akkouche; Ahcène Bounceur; Salvador Mir; Emmanuel Simeu

doi:10.1109/DTIS.2007.4449488

Minimization of functional tests by statistical modelling of analogue circuits

Nourredine Akkouche^*, Ahcène Bounceur, Salvador Mir, Emmanuel Simeu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults.

Original language	English
Title of host publication	Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007
Pages	35-40
Number of pages	6
DOIs	https://doi.org/10.1109/DTIS.2007.4449488
State	Published - 2007
Externally published	Yes
Event	2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 - Rabat, Morocco Duration: 2 Sep 2007 → 5 Sep 2007

Publication series

Name	Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007

Conference

Conference	2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007
Country/Territory	Morocco
City	Rabat
Period	2/09/07 → 5/09/07

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/DTIS.2007.4449488

Cite this

Akkouche, N., Bounceur, A., Mir, S., & Simeu, E. (2007). Minimization of functional tests by statistical modelling of analogue circuits. In Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 (pp. 35-40). Article 4449488 (Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007). https://doi.org/10.1109/DTIS.2007.4449488

Akkouche, Nourredine ; Bounceur, Ahcène ; Mir, Salvador et al. / Minimization of functional tests by statistical modelling of analogue circuits. Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007. 2007. pp. 35-40 (Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007).

@inproceedings{ecb8600229e34f3f8e4d78f15742aba8,

title = "Minimization of functional tests by statistical modelling of analogue circuits",

abstract = "In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults.",

author = "Nourredine Akkouche and Ahc{\`e}ne Bounceur and Salvador Mir and Emmanuel Simeu",

year = "2007",

doi = "10.1109/DTIS.2007.4449488",

language = "English",

isbn = "1424412781",

series = "Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007",

pages = "35--40",

booktitle = "Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007",

note = "2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 ; Conference date: 02-09-2007 Through 05-09-2007",

}

Akkouche, N, Bounceur, A, Mir, S & Simeu, E 2007, Minimization of functional tests by statistical modelling of analogue circuits. in Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007., 4449488, Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007, pp. 35-40, 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007, Rabat, Morocco, 2/09/07. https://doi.org/10.1109/DTIS.2007.4449488

Minimization of functional tests by statistical modelling of analogue circuits. / Akkouche, Nourredine; Bounceur, Ahcène; Mir, Salvador et al.
Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007. 2007. p. 35-40 4449488 (Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Mir, Salvador

AU - Simeu, Emmanuel

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N2 - In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults.

AB - In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults.

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U2 - 10.1109/DTIS.2007.4449488

DO - 10.1109/DTIS.2007.4449488

M3 - Conference contribution

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BT - Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007

T2 - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007

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ER -

Akkouche N, Bounceur A, Mir S, Simeu E. Minimization of functional tests by statistical modelling of analogue circuits. In Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007. 2007. p. 35-40. 4449488. (Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007). doi: 10.1109/DTIS.2007.4449488

Minimization of functional tests by statistical modelling of analogue circuits

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