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METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS

Aiman El-Maleh (Inventor)

King Fahd University of Petroleum & Minerals
Interdisciplinary Research Center for Intelligent Secure Systems
Department of Computer Engineering

Research output: Patent

Overview

Original language	English
Patent number	US10013296
State	Published - 2018

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El-Maleh, A. (2018). METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS. (Patent No. US10013296).

El-Maleh, Aiman (Inventor). / METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS. Patent No.: US10013296.

@misc{74b402f56dd5434786f24b2be39a582c,

title = "METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS",

author = "Aiman El-Maleh",

year = "2018",

language = "English",

type = "Patent",

note = "US10013296",

}

El-Maleh, A, METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS, Patent No. US10013296.

METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS. / El-Maleh, Aiman (Inventor).
Patent No.: US10013296.

Research output: Patent

TY - PAT

T1 - METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS

AU - El-Maleh, Aiman

PY - 2018

Y1 - 2018

M3 - Patent

M1 - US10013296

ER -

El-Maleh A, inventor. METHOD OF FAULT TOLERANCE IN COMBINATIONAL CIRCUITS. US10013296. 2018.

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