L3EP: Low latency, low energy program-And-verify for triple-level cell phase change memory

Ali Alsuwaiyan; Kartik Mohanram

doi:10.1109/NANOARCH.2017.8053710

L³EP: Low latency, low energy program-And-verify for triple-level cell phase change memory

Ali Alsuwaiyan
, Kartik Mohanram^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The increased capacity of multi-/triple-level cells (mlc/tlc) in phase change memory (pcm) comes at the cost of higher write latency and energy, primarily due to consecutive short programming pulses in the pcm program-And-verify (p&v) approaches. l³ep is a regression-based low latency, low energy tlc pcm p&v solution. l³ep reaches the target tlc state in just one (at most five) pulse(s) for up to 53% (>95%) of our comprehensive Monte Carlo (mc) simulations. l³ep also accelerates the naturally slow pcm crystallization process by packing crystallization pulses separated by short idle periods, and augmenting them with a single verify step. l³ep thus avoids unnecessary p&v verification steps resulting in faster crystallization. Results indicate that l³ep reduces the mean p&v latency (energy) by 2.4-15× (1.9-12.2×) in comparison to state-of-The-Art p&v approaches. l³ep is configurable through a comprehensive framework to compute critical p&v parameters to customize l³ep for multiple technology nodes.

Original language	English
Title of host publication	Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	27-32
Number of pages	6
ISBN (Electronic)	9781509060368
DOIs	https://doi.org/10.1109/NANOARCH.2017.8053710
State	Published - 28 Sep 2017
Externally published	Yes

Publication series

Name	Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

ASJC Scopus subject areas

Hardware and Architecture
Computer Networks and Communications

Access to Document

10.1109/NANOARCH.2017.8053710

Cite this

Alsuwaiyan, A., & Mohanram, K. (2017). L³EP: Low latency, low energy program-And-verify for triple-level cell phase change memory. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017 (pp. 27-32). Article 8053710 (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NANOARCH.2017.8053710

Alsuwaiyan, Ali ; Mohanram, Kartik. / L³EP : Low latency, low energy program-And-verify for triple-level cell phase change memory. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 27-32 (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017).

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title = "L3EP: Low latency, low energy program-And-verify for triple-level cell phase change memory",

abstract = "The increased capacity of multi-/triple-level cells (mlc/tlc) in phase change memory (pcm) comes at the cost of higher write latency and energy, primarily due to consecutive short programming pulses in the pcm program-And-verify (p\&v) approaches. l3ep is a regression-based low latency, low energy tlc pcm p\&v solution. l3ep reaches the target tlc state in just one (at most five) pulse(s) for up to 53\% (>95\%) of our comprehensive Monte Carlo (mc) simulations. l3ep also accelerates the naturally slow pcm crystallization process by packing crystallization pulses separated by short idle periods, and augmenting them with a single verify step. l3ep thus avoids unnecessary p\&v verification steps resulting in faster crystallization. Results indicate that l3ep reduces the mean p\&v latency (energy) by 2.4-15× (1.9-12.2×) in comparison to state-of-The-Art p\&v approaches. l3ep is configurable through a comprehensive framework to compute critical p\&v parameters to customize l3ep for multiple technology nodes.",

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Alsuwaiyan, A & Mohanram, K 2017, L³EP: Low latency, low energy program-And-verify for triple-level cell phase change memory. in Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017., 8053710, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Institute of Electrical and Electronics Engineers Inc., pp. 27-32. https://doi.org/10.1109/NANOARCH.2017.8053710

L³EP: Low latency, low energy program-And-verify for triple-level cell phase change memory. / Alsuwaiyan, Ali; Mohanram, Kartik.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 27-32 8053710 (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Alsuwaiyan A, Mohanram K. L³EP: Low latency, low energy program-And-verify for triple-level cell phase change memory. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 27-32. 8053710. (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017). doi: 10.1109/NANOARCH.2017.8053710