Low power high speed analog-to-digital converter for wireless communications

A. E. Hussein; M. I. Elmasry

doi:10.1145/330855.331016

Low power high speed analog-to-digital converter for wireless communications

A. E. Hussein^*, M. I. Elmasry

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip reliability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash/converter resolution by pre-calculating the most significant bits.

Original language	English
Pages (from-to)	113-116
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1145/330855.331016
State	Published - 2000
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1145/330855.331016

Cite this

@article{275cdd17d4424d04bf336366e921482c,

title = "Low power high speed analog-to-digital converter for wireless communications",

abstract = "A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip reliability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash/converter resolution by pre-calculating the most significant bits.",

author = "Hussein, \{A. E.\} and Elmasry, \{M. I.\}",

year = "2000",

doi = "10.1145/330855.331016",

language = "English",

pages = "113--116",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - Low power high speed analog-to-digital converter for wireless communications

AU - Hussein, A. E.

AU - Elmasry, M. I.

PY - 2000

Y1 - 2000

N2 - A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip reliability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash/converter resolution by pre-calculating the most significant bits.

AB - A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip reliability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash/converter resolution by pre-calculating the most significant bits.

UR - https://www.scopus.com/pages/publications/0033719081

U2 - 10.1145/330855.331016

DO - 10.1145/330855.331016

M3 - Conference article

AN - SCOPUS:0033719081

SN - 1066-1395

SP - 113

EP - 116

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

ER -

Low power high speed analog-to-digital converter for wireless communications

Abstract

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this